1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly, to a vertical surround gate metal-oxide semiconductor field-effect transistor (hereinafter referred to as xe2x80x9cMOSFETxe2x80x9d). The present invention further relates to a dynamic random access memory, an inverter circuit, and a static random access memory using such a vertical surround gate MOSFET. The present invention also relates to a method of manufacturing such a semiconductor device.
2. Description of the Background Art
FIG. 101 is a schematic diagram of a conventional planar type MOSFET. Referring to FIG. 101, a gate electrode 3 is provided on a P-type silicon substrate 1 with a gate insulating film 4 interposed therebetween. N-type source/drain regions 6a, 6b are provided on both sides of gate electrode 3 in the main surface of silicon substrate 1.
Operation of the conventional MOSFET will now be described. When a positive potential is applied to gate electrode 3, the following reaction occurs in the main surface of silicon substrate 1
xe2x80x83Bxe2x86x92Bxe2x88x92+h+
where B is boron, Bxe2x88x92 is a boron anion, and h+ is a hole.
More specifically, when a positive potential is applied to gate electrode 3, boron is separated into boron anions and holes. Boron anions are attracted to gate electrode 3. On the other hand, holes repulse gate electrode 3 to escape in silicon substrate 1, which in turn generates a depletion layer 17 in the main surface of a channel region of silicon substrate 1. Depletion layer 17 is a region where neither electrons nor holes exist, that is, where no carriers serving to make a current flow exist.
As a positive potential applied to gate electrode 3 is increased, depletion layer 17 is enlarged and its width Wd is increased. However, increase of the width Wd of depletion layer 17 is limited. The width of depletion layer 17 is determined by an impurity concentration. The larger the impurity concentration, the narrower the width Wd of the depletion layer. The smaller the impurity concentration, the wider the width Wd. The maximum value of the width Wd of depletion layer 17 is called maximum depletion layer width.
When the width Wd of depletion layer 17 reaches the maximum depletion layer width, an inversion layer 18 is formed on the surface of the channel region, rendering source 6a/drain 6b conductive.
When the integration density of a semiconductor device is increased, an area occupied by the MOSFET needs to be small.
FIG. 102 is a perspective view extracting and illustrating main portions of the conventional vertical type surround gate MOSFET improved so that an area occupied by the MOSFET may be made small.
Referring to FIG. 102, gate electrode 3 surrounds a plug-shaped silicon 5 with gate insulating film 4 interposed therebetween. Source region 6a is provided at an upper end of plug-shaped silicon 5, and drain region 6b is provided at a lower end thereof. Drain region 6b is formed in the main surface of the silicon substrate.
Aluminum interconnections 10a, 10b, and 10c are connected to source region 6a, gate electrode 3, and drain region 6b, respectively.
When a positive potential is applied to gate electrode 3, an inversion layer is generated on the sidewall surface of the plug-shaped silicon, causing a current to flow from source region 6a to drain region 6b. In other words, the current flows in the direction perpendicular to the silicon substrate.
Comparison is now made between an area occupied by the planar type MOSFET and an area occupied by the vertical type surround gate MOSFET.
Let L be a gate length of the planar type MOSFET, and W be a channel width of the planar type MOSFET, referring to FIG. 101, an occupied area Splanar of the channel region is
Splanar=Lxc2x7W
On the other hand, in the case of the vertical type surround gate MOSFET, referring to FIG. 103 (which is a simplification of FIG. 102), when the radius of the channel region is R, the channel width W is 2xcfx80R. An occupied area of the channel region is
Svertical=xcfx80R2=W2/4xcfx80
Therefore, when transistors having the gate length L equal to the channel width W are formed of a planar type MOSFET and a vertical type surround gate MOSFET, respectively, the ratio of respective occupied areas is
Svertical/Splanar=xc2xcxcfx80
More specifically, an occupied area of the vertical type surround gate MOSFET is {fraction (1/12)} or less of that of the planar type MOSFET.
If occupied areas of both the vertical type surround gate MOSFET and the planar type MOSFET are made equal, it is possible to increase W in the vertical type surround gate MOSFET. This is a first advantage of the vertical type surround gate MOSFET.
Referring to FIGS. 102 and 103, in the vertical type surround gate MOSFET, it is possible to deplete the entire channel by decreasing the radius of channel plug 5. Therefore, the vertical type surround gate MOSFET has advantages the same as those of a conventional SOI (Silicon-On-Insulator) MOSFET. Detailed description thereof will be given hereinafter.
If the entire channel can be depleted, it is possible to suppress a subthreshold current (a leakage current in a weakly inverted state), which in turn improves a circuit characteristic.
A subthreshold coefficient S is expressed by the following expression:
S=ln10xc2x7kT/qxc2x7(1+Cd/Cox)
where k is a Boltzmann constant, T is an absolute temperature, q is an elementary electric charge, Cd is a depletion layer capacitance of the MOSFET, and Cox is a gate insulating film capacitance.
As is clear from the above equation, when Cd=0 holds, the subthreshold coefficient S takes the minimum value
(ln10xc2x7kT/q=60 mV/dec).
FIG. 104 is a cross-sectional view of an SOIMOSFET. An SIO layer 15 is formed on a buried oxide film 16. Gate electrode 3 is formed on SOI layer 15 with gate insulating film 4 interposed therebetween. Source/drain regions 6a, 6b are formed on both sides of gate electrode 3 in the surface of SOI layer 15. In the figure, Wd is a depletion layer width, tSOI is the film thickness of SOI layer 15, and tBOX is the film thickness of buried oxide film 16.
When the entire SOI layer 15 is not depleted (that is, when Wd less than tSOI holds), the depletion layer capacitance Cd of the SOIMOSFET is, similar to the case of the MOSFET shown in FIG. 101, expressed by the following equation:
Cd=xcex5si/Wd
On the other hand, when the film thickness of buried oxide film 16 is sufficiently larger than that of SOI layer 15 (tBox greater than  greater than tSOI), and the entire SOI layer 15 is depleted (when it is in a fully depleted state, Wdxe2x89xa7tSOI), the depletion layer capacitance Cd is substantially 0. In the case of the SOIMOSFET, it is possible to make the depletion layer capacitance Cd zero by adjusting the film thickness of SOI layer 15, thereby suppressing a subthreshold current.
The above-described advantage of the SOIMOSFET can be implemented in the vertical type surround gate MOSFET. More specifically, when the fully depleted state is implemented in the vertical type surround gate MOSFET, the depletion layer capacitance Cd is 0 similar to the case of the SOIMOSFET. Since electric power lines extend in the radial direction, the phenomenon of which is unique to the surround type MOSFET, the depletion layer capacitance Cd is smaller than that of the MOSFET shown in FIG. 101 even in the state of incomplete depletion.
The following equation shows the relation between the radius R and the depletion layer capacitance Cd of the vertical type surround gate MOSFET, and FIG. 105 shows the equation in the form of graph.   Cd  =            ϵ      Si                                R          ·          ln                ⁢                  xe2x80x83                ⁢                  (                                    R              /              R                        -            Wd                    )                    )      
When R/Wd less than 1 holds, complete depletion of the channel can be implemented. Therefore, the depletion layer capacitance Cd is 0. Even if R/Wd greater than 1 holds, the depletion layer capacitance Cd is smaller than that of a bulk MOSFET shown in FIG. 100.
As described above, in the vertical type surround gate MOSFET, it is possible to make the depletion layer capacitance Cd zero by adjusting the radius of channel plug 5, which in turn makes it possible to suppress the subthreshold current. As a result, the vertical type surround gate MOSFET has a second advantage of improving a circuit characteristic.
A third advantage of the vertical type surround gate MOSFET is that the entire channel plug can be made an inversion layer, thereby increasing a drain current.
As described above, the vertical type surround gate MOSFET has three advantages.
FIGS. 106 to 109 are partial cross-sectional views of semiconductor device in respective steps of the manufacturing process of the conventional vertical type surround gate MOSFET.
Referring to FIG. 106, plug-shaped silicon 5 of the vertical type surround gate MOSFET is formed by anisotropically etching substrate 1. Plug-shaped silicon is cylindrical when represented in a perspective view as shown in FIG. 111.
Referring to FIG. 107, gate insulating film 4 is deposited on substrate 1 so as to cover plug-shaped silicon 5. Then, impurity ions are implanted into the surface of substrate 1 through gate insulating film 4 to form source region 6a and drain region 6b. 
Referring to FIG. 108, polysilicon 3 serving as a gate electrode is deposited on substrate 1.
Referring to FIGS. 108 and 109, polysilicon 3 is selectively etched to form gate electrode 3.
Referring to FIG. 110, an interlayer insulating film 2 is deposited on substrate 1 so as to cover gate electrode 3. A contact hole for exposing the surface of source region 6a, a contact hole for exposing a part of the surface of gate electrode 3, and a contact hole for exposing a part of the surface of drain region 6b are formed in interlayer insulating film 2. By connecting aluminum interconnections 10a, 10b, 10c to respective portions through these contact holes, the vertical type surround gate MOSFET shown in FIG. 102 is completed.
Although the conventional vertical type surround gate MOSFET had three advantages as described above, it also had the following problems.
Referring to FIG. 102, the diameter of plug-shaped silicon 5 must be made larger than a contact hole 8a so that aluminum interconnection 10a connected to drain region 6a and gate electrode 3 might not be short-circuited. Formation of large plug-shaped silicon 5 causes an area occupied by the device to increase. Formation of large plug-shaped silicon 5 also causes the channel plug not to be depleted completely, resulting in no inversion of the entire channel plug. Therefore, the conventional vertical type surround gate MOSFET was not able to fully enjoy the above-described three advantages.
One object of the present invention is to provide a vertical surround gate MOSFET improved so that an area occupied by the device can be substantially decreased.
Another object of the present invention is to provide a vertical type surround gate MOSFET improved so that a subthreshold current can be substantially suppressed, and that a circuit characteristic can be sufficiently enhanced.
Still another object of the present invention is to provide a vertical type surround gate MOSFET improved so that the entire channel portion can be made an inversion layer, and that a drain current can be substantially increased.
A further object of the present invention is to provide a dynamic random access memory using such a vertical type surround gate MOSFET.
A further object of the present invention is to provide an inverter circuit using such a vertical type surround gate MOSFET.
A further object of the present invention is to provide a static random access memory using such a vertical type surround gate MOSFET.
A further object of the present invention is to provide a method of manufacturing such a vertical type surround gate MOSFET.
According to a first aspect of the present invention, a semiconductor device controls a flow of majority carriers by a voltage applied to the gate. The semiconductor device includes a substrate having a main surface. A first conductive layer of a first conductivity type serving as one source/drain region is provided in the main surface of the substrate. A first interlayer insulating film is provided on the substrate. A gate electrode having an upper surface and a lower surface is provided on the first interlayer insulating film. A second interlayer insulating film is provided on the first interlayer insulating films so as to cover the gate electrode. A contact hole for exposing a part of the surface of the first conductive layer is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A sidewall surface of the contact hole is covered with a gate insulating film. A first semiconductor layer of a first conductivity type is formed on the surface of the first conductive layer in contact therewith up to the lower surface of the gate electrode in the contact hole. A channel semiconductor layer is formed on the surface of the first semiconductor layer in contact therewith up to the upper surface of the gate electrode in the contact hole. A second semiconductor layer of a first conductivity type serving as the other source/drain region is provided on the surface of the channel semiconductor layer in contact therewith.
According to a second aspect of the present invention, a semiconductor device controls a flow of majority carriers by a voltage applied to the gate. The semiconductor device includes a substrate having a main surface. A first conductive layer of a first conductivity type serving as one source/drain region is provided in the main surface of the substrate. A first interlayer insulating film is provided on the substrate. A gate electrode having an upper surface and a lower surface is provided on the first interlayer insulating film. A second interlayer insulating film is provided on the first interlayer insulating film so as to cover the gate electrode. A contact hole for exposing a part of the surface of the first conductive layer is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A sidewall surface of the contact hole is covered with a gate insulating film. A silicon thin film having a recessed portion in a portion of the contact hole is provided in contact with the first conductive layer so as to cover continuously the sidewall surface of the contact hole with the gate insulating film interposed therebetween. An insulating film is provided on the substrate so as to fill the recessed portion of the silicon thin film. The silicon thin film is divided into three portions of a cylindrical channel portion positioned at a portion surrounded by the gate electrode, a source region and a drain region sandwiching the channel portion from upper and lower sides. The thickness of the silicon thin film in the channel portion is equal to or less than the maximum depletion layer width.
According to a third aspect of the present invention, a semiconductor device controls a flow of majority carriers by a voltage applied to the gate. The semiconductor device includes a substrate having a main surface. A first conductive layer of a first conductivity type serving as one source/drain region is provided in the main surface of the substrate. A first interlayer insulating film is provided on the substrate. A gate electrode having an upper surface and a lower surface is provided on the first interlayer insulating film. A second interlayer insulating film is provided on the first interlayer insulating film so as to cover the gate electrode. A contact hole for exposing a part of the surface of the first conductive layer is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A sidewall surface of the contact hole is covered with a first gate insulating film. A silicon thin film is provided in contact with the first conductive layer so as to cover continuously an inner wall surface of the contact hole with the first gate insulating film interposed therebetween. The silicon thin film has a recessed portion having its bottom surface positioned below the lower surface of the gate electrode in the contact hole. The silicon thin film is divided into three portions of a cylindrical channel portion positioned at a portion surrounded by the first gate electrode, a source region and a drain region sandwiching the channel portion from upper and lower sides. The thickness of the silicon thin film in the channel portion is made equal to or less than the maximum depletion layer width. A second gate insulating film is provided on the substrate so as to cover the recessed portion of the silicon thin film. The semiconductor device further includes a second gate electrode filling the recessed portion of the silicon thin film so as to oppose the channel portion with the second gate insulting film interposed therebetween.
According to a fourth aspect of the present invention, a semiconductor device stores information by a gate transistor in a capacitor formed of a storage node, a capacitor insulating film, and a cell plate electrode, provided at a crossing point of a bit line and a word line. The semiconductor device includes a substrate having a main surface. A first impurity diffusion layer of a first conductivity type is provided in the main surface of the substrate by implantation of impurity of a first conductivity type. The first impurity diffusion layer serves as one source/drain region and also as the bit line. A first interlayer insulating film is provided on the substrate. A gate electrode having an upper surface and a lower surface is provided on the first interlayer insulating film. A second interlayer insulating film is provided on the first interlayer insulating film so as to cover the gate electrode. A contact hole for exposing a part of the surface of the first impurity diffusion layer is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A sidewall surface of the contact hole is covered with a gate insulating film. A first semiconductor layer of a first conductivity type is formed on the surface of the first impurity diffusion layer in contact therewith up to the lower surface of the gate electrode in the contact hole. A channel semiconductor layer is formed on the surface of the first semiconductor layer in contact therewith up to the upper surface of the gate electrode in the contact hole. A second conductive layer of a first conductivity type is provided on the channel semiconductor layer in contact with the surface of the channel semiconductor layer. The second conductive layer serves as the other source/drain region and also as the storage node. A capacitor insulating film is provided on the second conductive layer. A cell plate electrode is provided on the storage node with the capacitor insulating film interposed therebetween.
According to a fifth aspect of the present invention, a semiconductor device stores information by a gate transistor in a capacitor formed of a storage node, a capacitor insulating film, and a cell plate electrode, provided at a crossing point of a bit line and a word line. The semiconductor device includes a substrate having a main surface. A first conductive layer of a first conductivity type serving as one source/drain region is provided in the main surface of the substrate. A first interlayer insulating film is provided on the substrate. A gate electrode having an upper surface and a lower surface is provided on the first interlayer insulating film. A second interlayer insulating film is provided on the first interlayer insulting film so as to cover the gate electrode. A contact hole for exposing a part of the surface of the first conductive layer is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A sidewall surface of the contact hole is covered with a gate insulating film. A silicon thin film is provided in contact with the first conductive layer, so as to cover continuously the sidewall surface of the contact hole with the gate insulating film interposed therebetween. The silicon thin film includes a recessed portion having its bottom surface positioned below the lower surface of the gate electrode in the contact hole. The silicon thin film is divided into three portions of a cylindrical channel portion positioned at a portion surrounded by the gate electrode, one source/drain region positioned on the lower side and the other source/drain region positioned on the upper side, both sandwiching the channel portion from the opposite sides. The thickness of the silicon thin film in the channel portion is made equal to or less than the maximum depletion layer width. The other source/drain region is also used as a storage node. A capacitor insulating film is provided on the substrate so as to cover the recessed portion of the silicon thin film. The semiconductor device includes a cell plate electrode provided on the substrate so as to cover the silicon thin film with the capacitor insulating film interposed therebetween and to fill the recessed portion of the silicon thin film.
According to a sixth aspect of the present invention, a semiconductor device stores information by a gate transistor in a capacitor formed of a storage node, a capacitor insulating film, and a cell plate electrode, provided at a crossing point of a bit line and a word line. The semiconductor device includes a substrate having a main surface. A first conductive layer of a first conductivity type serving as one source/drain region is provided in the main surface of the substrate. A first interlayer insulating film is provided on the substrate. A gate electrode having an upper surface and a lower surface is provided on the first interlayer insulating film. A second interlayer insulating film is provided on the first interlayer insulating film so as to cover the gate electrode. A first contact hole for exposing a part of the surface of the first conductive layer is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A sidewall surface of the first contact hole is covered with a gate insulating film. A silicon thin film is provided in contact with the first conductive layer so as to cover continuously an inner wall surface of the first contact hole with the gate insulating film interposed therebetween. The silicon thin film includes a recessed portion having its bottom surface positioned below the lower surface of the gate electrode in the first contact hole. The silicon thin film is divided into three portions of a cylindrical channel portion positioned at a portion surrounded by the gate electrode, one source/drain region positioned on the lower side and the other source/drain region positioned on the upper side, both sandwiching the channel portion from the opposite sides. The thickness of the silicon thin film in the channel portion is made equal to or less than the maximum depletion layer width. A third interlayer insulating film is provided on the substrate so as to cover the silicon thin film. A second contact hole for exposing a part of the surface of the other source/drain region is provided in the third interlayer insulating film. A storage node is provided in contact with the other source/drain region so as to cover an inner wall surface of the second contact hole. A capacitor insulating film is provided on the substrate so as to cover the surface of the storage node. A cell plate electrode is provided on the substrate opposite to the storage node with the capacitor insulating film interposed therebetween so as to fill the second contact hole.
According to a seventh aspect of the present invention, a semiconductor device inverts logics of an input signal and an output signal. The semiconductor device includes a substrate, and a conductive layer provided on the substrate. A first interlayer insulating film is provided on the substrate so as to cover the conductive layer. A gate electrode having an upper surface and a lower surface is provided on the first interlayer insulating film. A second interlayer insulating film is provided on the substrate so as to cover the gate electrode. A first contact hole for exposing one part of the surface of the conductive layer is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A second contact hole for exposing another part of the surface of the conductive layer is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. An inner wall surface of the first contact hole is covered with a gate insulating film. An inner wall surface of the second contact hole is covered with a gate insulating film. A first p+ semiconductor layer serving as one source/drain region is formed on the surface of the conductive layer in contact with the one part thereof up to the lower surface of the gate electrode in the first contact hole. An nxe2x88x92 semiconductor layer is formed on the surface of the p+ semiconductor layer in contact therewith up to the upper surface of the gate electrode in the first contact hole. A second p+ semiconductor layer serving as the other source/drain region is provided on the nxe2x88x92 semiconductor layer in contact therewith. A first n+ semiconductor layer serving as one source/drain region is formed on the surface of the conductive layer in contact with the another part thereof up to the lower surface of the gate electrode in the second contact hole. A pxe2x88x92 semiconductor layer is formed on the surface of the first n+ semiconductor layer in contact therewith up to the upper surface of the gate electrode in the second contact hole. A second n+ semiconductor layer serving as the other source/drain region is provided on the pxe2x88x92 semiconductor layer in contact with the surface of the p+ semiconductor layer.
According to an eighth aspect of the present invention, a semiconductor device inverts logics of an input signal and an output signal. The semiconductor device includes a semiconductor substrate having a main surface. A field oxide film is formed in the main surface of the semiconductor substrate. An n+ impurity diffusion layer is provided in the main surface of the semiconductor substrate directly under the field oxide film. A gate electrode having an upper surface and a lower surface is provided on the field oxide film. An interlayer insulating film is provided on the semiconductor substrate so as to cover the gate electrode. A first contact hole for exposing one part of the surface of the n+ impurity diffusion layer is provided so as to penetrate through the interlayer insulating film, the gate electrode, and the field oxide film. A second contact hole for exposing another part of the surface of the n+ impurity diffusion layer is provided so as to penetrate through the interlayer insulating film, the gate electrode, and the field oxide film. An inner wall surface of the first contact hole is covered with the gate insulating film. An inner wall surface of the second contact hole is covered with a gate insulating film. A conductor film is provided in contact with the one part of the n+ impurity diffusion layer in the first contact hole. A first p+ semiconductor layer serving as one source/drain region is formed on the surface of the conductor film in contact therewith up to the lower surface of the gate electrode in the first contact hole. An nxe2x88x92 semiconductor layer is formed on the surface of the first p+ semiconductor layer in contact therewith up to the upper surface of the gate electrode in the first contact hole. A second p+ semiconductor layer serving as the other source/drain region is provided on the nxe2x88x92 semiconductor layer in contact therewith. A first n+ semiconductor layer serving as one source/drain region is formed on the surface of the n+ impurity diffusion layer in contact with the another part thereof up to the lower surface of the gate electrode in the second contact hole. A pxe2x88x92 semiconductor layer is formed on the surface of the first n+ semiconductor layer in contact therewith up to the upper surface of the gate electrode in the second contact hole. A second n+ semiconductor layer serving as the other source/drain region is provided on the pxe2x88x92 semiconductor layer in contact therewith.
According to a ninth aspect of the present invention, a semiconductor device inverts logics of an input signal and an output signal. The semiconductor device includes a semiconductor substrate having a main surface. A field oxide film is formed in the main surface of the semiconductor substrate. A p+ impurity diffusion layer and an n+ impurity diffusion layer are formed in the main surface of the semiconductor substrate with being separated from each other by the field oxide film. A first interlayer insulating film is provided on the semiconductor substrate. A gate electrode is provided on the first interlayer insulating film so as to cover the p+ impurity diffusion layer and the n+ impurity diffusion layer. A second interlayer insulating film is provided on the semiconductor substrate so as to cover the gate electrode. A first contact hole for exposing one part of the surface of the p+ impurity diffusion layer is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A second contact hole for exposing one part of the surface of the n+ impurity diffusion layer is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. An inner wall surface of the first contact hole is covered with a gate insulating film. An inner wall surface of the second contact hole is covered with a gate insulating film. A first p+ semiconductor layer serving as one source/drain region is provided on the surface of the p+ impurity diffusion layer in contact therewith up to the lower surface of the gate electrode in the first contact hole. An nxe2x88x92 semiconductor layer is formed on the surface of the first p+ semiconductor layer in contact therewith up to the upper surface of the gate electrode in the first contact hole. A second p+ semiconductor layer serving as the other source/drain region is provided on the n+ semiconductor layer. A first n+ semiconductor layer serving as one source/drain region is formed on the surface of the n+ impurity diffusion layer in contact therewith up to the lower surface of the gate electrode in the second contact hole. A pxe2x88x92 semiconductor layer is formed on the surface of the first n+ semiconductor layer in contact therewith up to the upper surface of the gate electrode in the second contact hole. A second n+ semiconductor layer serving as the other source/drain region is provided on the pxe2x88x92 semiconductor layer in contact therewith. An end portion of the second p+ semiconductor layer and an end portion of the second n+ semiconductor layer are in contact with each other at an upper portion of the field oxide film. The semiconductor device further includes a connection member electrically connecting the surface of the second p+ semiconductor layer and the surface of the second n+ semiconductor layer.
According to a tenth aspect of the present invention, a semiconductor device serves as a logic circuit in a cooperative operation of a first transistor and a second transistor. The semiconductor device includes a substrate, and an SiO2 layer provided on the substrate. A semiconductor layer having an upper surface and a lower surface is provided on the SiO2 layer. A gate electrode of the first transistor is provided on the semiconductor layer with an insulating film interposed therebetween. The semiconductor device includes a pair of source/drain regions of the first transistor provided in the semiconductor layer and spaced from each other on the opposite sides of the gate electrode. A contact hole for exposing one part of the surface of the substrate is provided at a position distant from the gate electrode of the first transistor so as to penetrate through one of the source/drain regions and the SiO2 layer. An inner wall surface of the contact hole is covered with a gate insulating film of the second transistor. One source/drain layer of the second transistor is formed on the surface of the substrate in contact therewith up to the lower surface of the semiconductor layer in the contact hole. A channel layer of the second transistor is formed on the surface of the one source/drain layer of the second transistor in contact therewith up to the upper surface of the semiconductor layer in the contact hole. The other source/drain layer of the second transistor is provided on the channel layer of the second transistor in contact therewith.
According to an eleventh aspect of the present invention, a semiconductor device inverts logics of an input signal and an output signal in a cooperative operation of a first transistor and a second transistor. The semiconductor device includes a substrate and a first insulating film provided on the substrate. A gate electrode of the first transistor having an upper surface and a lower surface is provided on the first insulating film. A second insulating film is provided on the substrate so as to cover the gate electrode of the first transistor. A contact hole for exposing one part of the surface of the substrate is provided so as to penetrate through the gate electrode of the first transistor and the second insulating film. One source/drain layer of the second transistor is provided in the main surface of the substrate directly under the contact hole. An inner wall surface of the contact hole is covered with a gate insulating film of the second transistor. A channel layer of the second transistor is formed on the surface of the one source/drain layer of the second transistor in contact therewith up to the upper surface of the gate electrode in the contact hole. The other source/drain layer of the second transistor is provided on the channel layer of the second transistor in contact therewith.
According to a twelfth aspect of the present invention, a semiconductor device stores information in a cooperative operation of four transistors. The semiconductor device includes a flip-flop formed using two inverter circuits according to the ninth aspect, and two transistors.
According to a thirteenth aspect of the present invention, a semiconductor device stores information in a cooperative operation of four transistors. The semiconductor device is characterized in that a transistor according to the first aspect of the present invention is used as an access transistor.
According to a fourteenth aspect of the present invention, a semiconductor device stores information in a cooperative operation of four transistors. The semiconductor device is characterized in that transistors according to the first aspect of the present invention are used as an access transistor and a load transistor.
In a method of manufacturing a semiconductor device according to a fifteenth aspect of the present invention, a first conductive layer is formed including impurity of a first conductivity type and serving as one source/drain region in the main surface of a substrate. A first interlayer insulating film is formed on the substrate. A gate electrode having an upper surface and a lower surface is formed on the first interlayer insulating film. A second interlayer insulating film is formed on the substrate so as to cover the gate electrode. A contact hole is formed penetrating through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film into the surface of the first conductive layer. A sidewall surface of the contact hole is covered with a gate insulating film. A semiconductor layer is formed on the substrate in contact with the surface of the first conductive layer so as to fill the contact hole. Impurity of a first conductivity type is implanted into the surface of the semiconductor layer. The impurity implanted into the surface of the semiconductor layer is diffused in the semiconductor layer, and the impurity included in the first conductive layer is diffused from the first conductive layer to the semiconductor layer, whereby the other source/drain region and a channel region sandwiched by the other source/drain region and the one source/drain region are formed in the semiconductor layer.
According to a method of manufacturing a semiconductor device in accordance with a sixteenth aspect of the present invention, a semiconductor device controlling a flow of majority carriers by a voltage applied to the gate is manufactured. A silicon nitride film is formed on the surface of a substrate. A first conductive layer including impurity of a first conductivity type and serving as one source/drain region is formed in the main surface of the substrate by implanting impurity into the surface of the substrate through the silicon nitride film. A first interlayer insulating film is formed on the substrate so as to cover the silicon nitride film. A gate electrode having an upper surface and a lower surface is formed on the first interlayer insulating film. A second interlayer insulating film is formed on the substrate so as to cover the gate electrode. A contact hole is formed penetrating through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film into the surface of the silicon nitride film. A sidewall surface of the contact hole is oxidized to form a gate insulating film. An exposed surface of the silicon nitride film is etched for exposure of the surface of the first conductive layer. A semiconductor layer is formed on the substrate in contact with the surface of the exposed first conductive layer so as to fill the contact hole. Impurity of a first conductivity type is implanted into the surface of the semiconductor layer. The impurity implanted into the surface of the semiconductor layer is diffused in the semiconductor layer, and the impurity included in the first conductive layer is diffused from the first conductive layer to the semiconductor layer, whereby the other source/drain region and a channel region sandwiched by the other source/drain region and the one source/drain region are formed in the semiconductor layer.
A method of manufacturing a semiconductor device according to a seventeenth aspect of the present invention relates to a method of manufacturing a semiconductor device controlling a flow of majority carriers by a voltage applied to the gate. A first source/drain drawing-out electrode is formed in the main surface of the substrate for drawing out a source/drain electrode to an external terminal. A first interlayer insulating film, a gate electrode and a second interlayer insulating film are sequentially deposited on the substrate. A contact hole is formed penetrating through the first interlayer insulating film, the gate electrode and the second interlayer insulating film for exposing one part of the surface of the first source/drain drawing-out electrode. An inner wall surface of the contact hole is covered with a gate insulating film. A first epitaxial silicon layer including impurity of a first conductivity type, a second epitaxial silicon layer including impurity of a second conductivity type, and a third epitaxial silicon layer including impurity of a first conductivity type are sequentially formed in the contact hole. A second source/drain drawing-out electrode is formed on the third epitaxial silicon layer.
A method of manufacturing a semiconductor device according to an eighteenth aspect of the present invention relates to a method of manufacturing a semiconductor device controlling a flow of majority carriers by a voltage applied to the gate. Formed in the main surface of a substrate is a first conductive layer including impurity of a first conductivity type and serving as one source/drain region. A first interlayer insulating film is formed on the substrate. A gate electrode having an upper surface and a lower surface is formed on the first interlayer insulating film. A second interlayer insulating film is formed on the substrate so as to cover the gate electrode. A contact hole is formed penetrating through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film into the surface of the first conductive layer. A sidewall surface of the contact wall is covered with a gate insulating film. A semiconductor film is formed on the substrate so as to cover the surface of the first conductive layer and an inner wall surface of the contact wall. Impurity of a first conductivity type is implanted into the surface of the semiconductor film by a rotational ion implantation method. The impurity implanted into the surface of the semiconductor film is diffused in the semiconductor film, and the impurity included in the first conductive layer is diffused from the first conductive layer to the semiconductor film, whereby the other source/drain region and a channel region sandwiched by the other source/drain region and the one source/drain region are formed in the semiconductor film. An insulating film fills the contact hole in contact with the semiconductor film.
A method of manufacturing a semiconductor device according to a nineteenth aspect of the present invention relates to a method of manufacturing a semiconductor device controlling a flow of majority carriers by a voltage applied to the gate. Formed in the main surface of the substrate is a first conductive layer including impurity of a first conductivity type and serving as one source/drain region. A first interlayer insulating film is formed on the substrate. A gate electrode having an upper surface and a lower surface is formed on the first interlayer insulating film. A second interlayer insulating film is formed on the substrate so as to cover the gate electrode. A contact hole is formed penetrating through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film into the surface of the first conductive layer. A sidewall surface of the contact hole is covered with a gate insulating film. A semiconductor film is formed on the substrate so as to cover the surface of the first conductive layer and an inner wall surface of the contact hole. A first insulating film is formed on the sidewall surface of the contact hole with the semiconductor film interposed therebetween. Impurity of a first conductivity type is implanted into the surface of the semiconductor film in a direction perpendicular to the substrate with the first insulating film used as a mask. The impurity implanted into the surface of the semiconductor film is diffused in the semiconductor film, and the impurity included in the first conductive layer is diffused from the first conductive layer to the semiconductor film, whereby the other source/drain region and a channel region sandwiched by the other source/drain region and the one source/drain region are formed in the semiconductor film. A second insulating film fills the contact hole with the first insulating film and the semiconductor film interposed therebetween.
A method of manufacturing a semiconductor device according to a twentieth aspect of the present invention relates to a method of manufacturing a semiconductor device controlling a flow of majority carriers by a voltage applied to the gate. Formed in the main surface of the substrate is a first conductive layer including impurity of a first conductivity type and serving as one source/drain region. A first interlayer insulating film is formed on the substrate. A gate electrode having an upper surface and a lower surface is formed on the first interlayer insulating film. A second interlayer insulating film is formed on the substrate so as to cover the gate electrode. A contact hole is formed penetrating through the first interlayer insulating film, the gate electrode and the second interlayer insulating film into the surface of the first conductive layer. A sidewall surface of the contact wall is covered with a gate insulating film. A semiconductor film is formed on the substrate so as to cover the surface of the first conductive layer and an inner wall surface of the contact hole. An insulating film fills the contact hole in contact with the semiconductor film. Impurity of a first conductivity type is implanted into the surface of the semiconductor film. The impurity implanted into the surface of the semiconductor film is diffused in the semiconductor film, and the impurity included in the first conductive layer is diffused from the first conductive layer to the semiconductor film, whereby the other source/drain region and a channel region sandwiched by the other source/drain region and the one source/drain are formed in the semiconductor film.
A method of manufacturing a semiconductor device according to a twenty-first aspect of the present invention relates to a method of manufacturing a semiconductor device controlling a flow of majority carriers by a voltage applied to the gate. Formed in the main surface of a substrate is a first conductive layer including impurity of a first conductivity type and serving as one source/drain region. A first interlayer insulating film is formed on the substrate. A first gate electrode having an upper surface and a lower surface is formed on the first interlayer insulating film. A second interlayer insulating film is formed on the substrate so as to cover the first gate electrode. A contact hole is formed penetrating through the first interlayer insulating film, the first gate electrode, and the second interlayer insulating film into the surface of the first conductive layer. A sidewall surface of the contact hole is covered with a first gate insulating film. A semiconductor film is formed in contact with the surface of the first conductive layer so as to cover an inner wall surface of the contact hole with the first gate insulating film interposed therebetween. Formed in the semiconductor film are one source/drain region in contact with the first conductive layer, a channel region connected to the one source/drain region, and the other source/drain region connected to the channel region. A second gate insulating film covering an inner wall surface of the contact hole is formed on the substrate with the semiconductor film interposed therebetween. A second gate electrode fills the contact hole so as to oppose the semiconductor film with the second gate insulating film interposed therebetween.
A method of manufacturing a semiconductor device according to a twenty-second aspect of the present invention relates to a method of manufacturing a semiconductor device controlling a flow of majority carriers by a voltage applied to the gate. Formed in the main surface of a substrate is a first conductive layer including impurity of a first conductivity type and serving as one source/drain region. A first interlayer insulating film is formed on the substrate. A gate electrode having an upper surface and a lower surface is formed on the first interlayer insulating film. A second interlayer insulating film is formed on the substrate so as to cover the gate electrode. A contact hole is formed penetrating through the first interlayer insulating film, the gate electrode and the second interlayer insulating film into the surface of the first conductive layer. A sidewall surface of the contact hole is covered with a gate insulating film. A semiconductor layer is formed on the substrate so as to fill the contact hole. One source/drain region of a first conductivity type connected to the first conductive layer is formed in the semiconductor layer. A channel region of a second conductivity type connected to the one source/drain region is formed in the semiconductor layer. A region of a low concentration of the other source/drain region of a first conductivity type connected to the channel region is formed in the semiconductor layer. A region of a high concentration of the other source/drain region of a first conductivity type is formed in the semiconductor layer so as to be connected to the region of a low concentration.
The semiconductor device according to the first aspect of the present invention occupies a small area since a vertical type surround gate is employed.
In the semiconductor device according to the second aspect of the present invention, it is possible to completely deplete the entire channel since the thickness of the silicon thin film in the channel is equal to or less than the maximum depletion layer width or less.
In the semiconductor device according to the third aspect of the present invention, it is possible to reduce an off current of a transistor and to improve an on current of the transistor since the device includes two gate electrodes.
In the semiconductor device according to the fourth aspect of the present invention, that is, in a dynamic random access memory, an area occupied by the DRAM is small since a contact hole transistor is used.
In the semiconductor device according to the fifth and sixth aspects of the present invention, that is, in a DRAM, an area occupied by the DRAM is small since a contact hole transistor is used.
In the inverter circuit according to the seventh aspect of the present invention, an area occupied by the inverter circuit is small since a contact hole transistor is used.
In the inverter circuit according to the eighth aspect of the present invention, the surface of the semiconductor substrate can be effectively used since the inverter circuit is formed on the field oxide film.
In the inverter circuit according to the ninth aspect of the present invention, contact is easily made and an area occupied by the inverter circuit is small since Vout is provided at the upper portion of the substrate.
In the logic circuit according to the tenth aspect of the present invention, an area occupied by the logic circuit is small since an SOI transistor and a contact hole transistor are used to form the inverter circuit.
In the inverter circuit according to the eleventh aspect of the present invention, an area occupied by the inverter circuit can be made small since an MOS transistor and a contact hole transistor are combined to form the inverter circuit.
In the semiconductor device according to the twelfth, thirteenth, and fourteenth aspects of the present invention, a static random access memory occupying a small area can be obtained.
According to the method of manufacturing a semiconductor device of the fifteenth aspect of the present invention, the impurity implanted into the surface of the semiconductor layer is diffused in the semiconductor layer and the impurity included in the first conductive layer is diffused from the first conductive layer to the semiconductor layer, whereby the other source/drain region and a channel region sandwiched by the other source/drain region and the one source/drain region are formed in the semiconductor layer. Therefore, the source/drain region and the channel region can be formed simultaneously by one time thermal diffusion.
According to the method of manufacturing a semiconductor device of the sixteenth aspect of the present invention, since the gate insulating film is formed by oxidation of the sidewall surface of the contact hole, the method of forming the gate insulating film can be facilitated.
According to the method of manufacturing a semiconductor device of the seventeenth aspect of the present invention, since the channel region is formed by epitaxial growth, crystallization of the channel region is enhanced, which in turn improves the transistor characteristics. Since the conductivity type of the semiconductor can be changed by only changing gas at the time of growth of an epitaxial layer, the process can be simplified.
According to the method of manufacturing a semiconductor device of the eighteenth aspect of the present invention, since impurity of a first conductivity type is implanted into the surface of the semiconductor film by a rotational ion implantation method, the impurity can be implanted into the inner wall surface of the contact hole.
According to the method of manufacturing a semiconductor of the nineteenth aspect of the present invention, since impurity of a first conductivity type is implanted into the surface of the semiconductor film with the first insulating film used as a mask in a direction perpendicular to the substrate, the impurity is not implanted into the channel portion even if the implantation angle is slightly offset. As a result, a leakage current between source and drain is not generated.
According to the method of manufacturing a semiconductor device of the twentieth aspect of the present invention, impurity of a first conductivity type is implanted into the surface of the semiconductor film after filling the contact hole with the insulating film in contact with the semiconductor film. Then, the impurity implanted into the surface of the semiconductor film is diffused in the semiconductor film to form the other source/drain region. Therefore, the impurity is not implanted into the bottom portion of the semiconductor film. As a result, the impurity is not diffused into the channel region by heat treatment to be applied later, not causing the short channel effect. Leakage current between source and drain is not generated.
According to the method of manufacturing a semiconductor device of the twenty-first aspect of the present invention, since a transistor having two gate electrodes can be formed, it is possible to reduce the off current of the transistor and to improve the on current of the transistor.
According to the method of manufacturing a semiconductor device of the twenty-second aspect of the present invention, since the source/drain, the channel, the LDD portion are formed by high energy ion implantation, the formation can be facilitated.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.